SOC Physical Design Engineer (Experienced)

● Floor planning, powerplan synthesis, clock tree synthesis, timing closure, routing, and post- route optimization
● Physical verification signoff including DRC, LVS, ERC, Antenna and ESD
● Coordinate cross- site communication and coordination among internal supporting groups
● ASIC physical implementation by using automatic place and route tools

● BS or MS degree in EE or CS related
● Familiar with Cadence Innovus or Synopsys Fusion Compiler flow
● Candidate with 8 years experience or more will be considered for senior manger/technical lead position
● Candidate with lesser experience will be considered for junior position
● Good English communication skills
● Excellent team and interpersonal skills
● Min 2 years working experience
● Familiar with timing closure, IR drop analysis and physical verification

- Intensive training on the job.
- Opportunities for self- development and career advancement
- Attractive salary, allowance and bonus with annual revision.
- People values, social responsibility, and sustainability.
- Strong team spirit in an entrepreneurial environment of a growing company.

Cập nhật gần nhất lúc: 2024-05-10 06:35:02